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rev. 0.1 /jul. 2012 1 204pin ddr3l sdram ecc sodimm *sk hynix reserves the right to change pr oducts or specifications without notice. ddr3l sdram ecc so-dimms based on 2gb c-die HMT325A7CFR8A hmt351a7cfr8a
rev. 0.1 / jul. 2012 2 revision history revision no. history draft date remark 0.1 initial release jul. 2012
rev. 0.1 / jul. 2012 3 description 204pin ecc-so-udimms (72bit-wide, double data ra te synchronous dram small outline dual in-line memory modules) are low power, high-speed oper ation memory modules. these ecc-sd-udimms are intended for use as computing memory when installe d in systems such as embe dded systems and servers, workstations. ecc-so-dimms are running at 533/667/800 mhz clock speed and offering. 8500/10600/ 12800 mb/s bandwidth on the primary data bus. features ? power supply: vdd=1.35v (1.283v to 1.45v) ? vddq = 1.35v (1.283v to 1.45v) ? vddspd=3.0v to 3.6v ? functionality and operations comply with the ddr3 sdram datasheet ? 8 internal banks ? data transfer rates: pc3-12800, pc3-10600, pc3-8500 ? bi-directional differential data strobe ? 8 bit pre-fetch ? burst length (bl) switch on-the-fly: bl 8 or bc (burst chop) 4 ? on die termination (odt) supported ? this product is in compliance with the rohs directive. ordering information part number density organization component composition # of ranks HMT325A7CFR8A-g7/h9/pb 2gb 256mx72 256mx8(h5tc2g83cfr)*9 1 hmt351a7cfr8a-g7/h9/pb 4gb 512mx72 256mx8(h5tc2g83cfr)*18 2
rev. 0.1 / jul. 2012 4 key parameters * sk hynix dram devices support opti onal downbinning to cl9 and cl7. spd setting is programmed to match. speed grade address table mt/s grade tck (ns) cas latency (tck) trcd (ns) trp (ns) tras (ns) trc (ns) cl-trcd-trp ddr3l-1066 -g7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 ddr3l-1333 -h9 1.5 9 13.5 (13.125)* 13.5 (13.125)* 36 49.5 (49.125)* 9-9-9 ddr3l-1600 -pb 1.25 11 13.75 (13.125)* 13.75 (13.125)* 35 48.75 (48.125)* 11-11-11 grade frequency [mhz] remark cl5 cl6 cl7 cl8 cl9 cl10 cl11 -g7 667 800 1066 1066 -h9 667 800 1066 1066 1333 1333 -pb 667 800 1066 1066 1333 1333 1600 2gb(1rx8) 4gb(2rx8) refresh method 8k/64ms 8k/64ms row address a0-a14 a0-a14 column address a0-a9 a0-a9 bank address ba0-ba2 ba0-ba2 page size 1kb 1kb
rev. 0.1 / jul. 2012 5 pin descriptions pin name description num ber pin name description num ber ck0 clock input, positive line 1 odt[1:0] on die termination inputs 2 ck0 clock input, negative line 1 dq[63:0] data input/output 64 ck1 clock input, positive line 1 cb[7 :0] data check bits input/output 8 ck1 clock input, negative line 1 dqs[8:0] data strobes 9 cke[1:0] clock enables 2 dqs [8:0] data strobes, negative line 9 ras row address strobe 1 dm[8:0] data masks 9 cas column address strobe 1 we write enable 1 s [3:0] chip selects 4 event reserved for optional hardware temperature event pin 1 a[9:0],a11, a[15:13] address inputs 14 a10/ap address input/autoprecharge 1 reset reset and sdram control pin 1 a12/bc address input/burst chop 1 v dd power supply xx ba[2:0] sdram bank addresses 3 v ss ground xx scl serial presence detect (spd) clock input 1 v refdq reference voltage for dq 1 sda spd data input/output 1 v refca reference voltage for ca 1 sa[1:0] spd address inputs 2 v tt termination voltage 2 par_in parity bit for the address and control bus 1 v ddspd spd power 1 err_out parity error found on the address and control bus 1 total : 204
rev. 0.1 / jul. 2012 6 input/output functional descriptions symbol type polarity function ck0 in positive edge positive line of the differential pair of system clock inputs that drives input to the on- dimm clock driver (72b-so-rdimm), on-di mm pll (72b-so-cdimm), or to dram on rank 0 (72b-sd-dimm). ck0 in negative edge negative line of the differential pair of syst em clock inputs that drives input to the on- dimm clock driver (72b-so-rdimm), on-di mm pll (72b-so-cdimm), or to dram on rank 0 (72b-sd-dimm). ck1 in positive edge positive line of a se condary differential pair of system clock inputs. teminated but not used on 72b-so-rdimms or 72b-so-cdimms. connected to drams on rank 1 or 72b- sd-dimms. ck0/ck0 ck1/ck1 in negative edge negative line of a secondary differential pair of system clock inputs. teminated but not used on 72b-so-rdimms or 72b-so-cdimms. connected to drams on rank 1 or 72b- sd-dimms. cke[1:0] in active high cke high activates, and cke low deactivates internal clock signal s, and device input buffers and output drivers of the sdra ms. taking cke low provieds precharge power-down and self refres h operation (all banks idle), or active power down (row active in any bank). connected to the registering clock driver on 72b-so- rdimms, connected to drams on 72b-so-cdimms and 72b-so-dimms. s [1:0] in active low enables the command decoders for the asso ciated rank of sdram when low and dis- ables decoders when high. when decoders are disabled, new commands are ignored and previous operations continue. connec ted to sdrams on 72b-sd-cdimms and 72b- so-dimms. for 72b-so-rdimms, the combinations of these input signals perform unique functions, including disabling all outputs (except cke and odt) of the register(s) on the dimm or accessing internal control words in the register device(s). for modules with two registers, s[3:2] operate similarly to s[1:0] for the second set of register out- puts or register control words. odt[1:0] in active high on-die termination control signals. connected to sdrams on 72b-so-cdimms and 72b- so-dimms, connected to the register ing clock driver on 72b-so-rdimms. r as , cas , we in active low when sampled at the positive rising edge of the clock. cas , ras , and we define the operation to be executed by the sdram. connected to sdrams on 72b-so-cdimms and 72b-so-dimms, connected to the registering clock driver on 72b-so-rdimms. v refdq supply reference voltage fo r dq0-dq63 and cb0-cb7. v refca supply reference voltage for a0-a15, ba0-ba2, ras , cas , we, s0 , s1 , cke0, cke1, par_in, odt0 and odt1. ba[2:0] in ? selects which sdram internal bank of eight is activated. ba0 - ba2 define to which bank an active, read, write or precharge commnad is being applied. bank address also derermines mode register is to be accessed during an mrs cycle. connected to sdrams on 72b-so-cdimms and 72b-so-dimms, connected to the registering clock driver on 72b-so-rdimms. a[9:0], a10/ap, a11, a12/bc a[15:13] in ? provided the row address for active commna ds and the column address and auto pre- charge bit for read/write commands to select one lacation out of the memory array in the respective bank. a10 is sampled during a precharge command to detemine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba. a12 is also utilized for bl 4/8 identifica- tion for ?bl on the fly? during cas command. the address inputs also provied the op- code during mode register set commands. connected to sdrams on 72b-so-cdimms and 72b-so-dimms, connected to the regi stering clock driver on 72b-so-rdimms.
rev. 0.1 / jul. 2012 7 dq[63:0] cb[7:0] i/o ? data and check input/output pins. dm[8:0] in active high mask write data when high, issued concurrently with input data. v dd , v ss supply power and ground for the ddr3 sdram input buffers and core logic. v tt supply termination voltage for address/command/control/clock nets. dqs1[7:0] i/o positive edge positive line of the differential data strobe for input and output data dqs[7:0], dqs[7:0] i/o negative edge negative line of the differential data strobe for input and output data sa[1:0] in ? these signals are tied at the system planar to either v ss or v ddspd to configure the serial spd eeprom address range. sda i/o ? this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v ddspd on the system pl anar to act as a pullup. scl in ? this signal is used to clock data into and out of the spd eeprom. a resistor may be con- nected from the scl bus time to v ddspd on the system planar to act as a pullup. event out (open drain) active low this signal indicates that a thermal event has been detected in the thermal sensing device.the system should guarantee the electrical level requirement is met for the event pin on ts/spd part. v ddspd supply serial eeprom positive power supply wired to a separate power pin at the connector which supports from 3.0 volt to 3.6 volt (nominal 3.3v) operation. reset in the reset pin is connected to the reset pi n on the register (72b-sd-rdimm) and to the reset pin on the sdrams (all modules). when low, all register outputs will be driven low and the clock driver clocks to th e drams and register(s) will be set to low lever (the clock driver will remain synchronized with the input clock). par_in in parity bit for the address and control bus. (?1?: odd, ?0?: even). not used on 72b-so- dimms or 72b-so-cdimms. err_out out (open drain) parity error detected on the address and cont rol bus. a resistor may be connected from err_out bus line to v on the system planner to act as a pull up. not used on 72b-so- dimms or 72b-so-cdimms. symbol type polarity function
rev. 0.1 / jul. 2012 8 pin assignments pin # front side pin # back side pin # front side pin # back side pin # front side pin # back side pin # front side pin # back side 1 v ref dq 2 v ss 53 v ss 54 dq28 103 a3 104 a4 155 v ss 156 dqs5 3 v ss 4 dq4 55 dq24 56 dq29 105 a1 106 a2 157 dm5 158 v ss 5 dq0 6 dq5 57 dq25 58 v ss 107 a0 108 ba1 159 dq42 160 dq46 7dq18 v ss 59 dm3 60 dqs 3 109 v dd 110 v dd 161 dq43 162 dq47 9 v ss 10 dqs 0 61 v ss 62 dqs3 111 ck0 112 par_in , nc, ck1 163 v ss 164 v ss 11 dm0 12 dqs0 63 v ss 64 v ss 113 ck0 114 err_out , nc, ck1 165 dq48 166 dq52 13 dq2 14 v ss 65 dq26 66 dq30 115 v dd 116 v dd 167 dq49 168 dq53 15 dq3 16 dq6 67 dq27 68 dq31 117 a10/ap 118 s3 169 v ss 170 v ss 17 v ss 18 dq7 69 cb0 70 v ss 119 ba0 120 s2 171 dqs 6 172 dm6 19 dq8 20 v ss 71cb172cb4121 we 122 ras 173 dqs6 174 dq54 21 dq9 22 dq12 key 123 v dd 124 v dd 175 dq50 176 dq55 23 v ss 24 dq13 73 v ss 74 cb5 125 cas 126 odt0 177 dq51 178 v ss 25 dqs 1 26 v ss 75 dqs 8 76 dm8 127 s0 128 odt1 179 v ss 180 dq60 27 dqs1 28 dm1 77 dqs8 78 v ss 129 s1 130 a13 181 dq56 182 dq61 29 v ss 30 reset 79 v ss 80 cb6 131 v dd 132 v dd 183 dq57 184 v ss 31 dq10 32 v ss 81 cb2 82 cb7 133 dq32 134 dq36 185 v ss 186 dqs 7 33 dq11 34 dq14 83 cb3 84 v ref ca 135 dq33 136 dq37 187 dm7 188 dqs7 35 v ss 36 dq15 85 v dd 86 v dd 137 v ss 138 v ss 189 v ss 190 v ss 37 dq16 38 v ss 87 cke0 88 a15 139 dqs 4 140 dm4 191 dq58 192 dq62 39 dq17 40 dq20 89 cke1 90 a14 141 dqs4 142 dq38 193 dq59 194 dq63 41 v ss 42 dq21 91 ba2 92 a9 143 v ss 144 dq39 195 v ss 196 v ss 43 dqs 2 44 dm2 93 v dd 94 v dd 145 dq34 146 v ss 197 sa0 198 event 45 dqs2 46 v ss 95 a12/bc 96 a11 147 dq35 148 dq44 199 vdd spd 200 sda 47 v ss 48 dq22 97 a8 98 a7 149 v ss 150 dq45 201 sa1 202 scl 49 dq18 50 dq23 99 a5 100 a6 151 dq40 152 v ss 203 v tt 204 v tt 51 dq19 52 v ss 101 v dd 102 v dd 153 dq41 154 dqs 5 nc = no connect notes on following page for differences of 72b-so-rdimms, 72b-so-cdimms, 72b-so-dimms
rev. 0.1 / jul. 2012 9 functional block diagram 2gb, 256mx72 module( 1 rank of x 8) dqs0 dqs0 dm0 dq[0, 7] dqs dqs dm dq d0 ras cas s0 we ck0 ck0 cke0 odt0 ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq d4 ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs2 dqs2 dm2 dq[16, 23] dqs dqs dm dq d1 ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq d5 ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs2 dqs2 dm2 dq[32, 39] dqs dqs dm dq d2 ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq d6 ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs3 dqs3 dm3 dq[48, 55] dqs dqs dm dq d3 ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq d7 ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs1 dqs1 dm1 dq[8, 15] dqs3 dqs3 dm3 dq[24, 31] dqs5 dqs5 dm5 dq[40, 47] dqs7 dqs7 dm7 dq[56, 63] d0?d8 v dd spd spd/ts d0?d8 v ref ca v tt d0?d8 v dd a2 sda scl wp a1 a0 scl sa0 sa1 vtt v ref dq v ss ck0 ck1 ck0 ck1 s1 odt1 d0?d8 d0?d8 d0?d8 nc nc notes 1. dq - to - i/o wiring may be changed within a byte 2. zq resistors are 240 ohms +/- 1%. for all other resi stor values refer to the appropriate wiring diagram. 3. the connected of the serial pd to event (option 1) or to ground (option 2) is realized by resistor options. option 2 serial spd cke1 event reset temp sensor d0-d8 nc terminated near card edge dqs8 dqs8 dm8 cb[0, 7] dqs dqs dm dq d8 ras cas cs we ck ck cke odt a[o:n]/ba[o:n] sa2 a2 sda scl a1 a0 scl sa0 sa1 option 1 integrated thermal sensor in spd sa2 event event sensor pd w/integrated thermal sensor sensor pd no thermal sensor a[o:n]/ba[o:n] vtt vtt
rev. 0.1 / jul. 2012 10 4gb, 512mx72 modu le(2rank of x8) dqs0 dqs0 dm0 dq[0, 7] dqs dqs dm dq d0 ras cas s0 we ck0 ck0 cke0 odt0 a[o:n]/ba[o:n] 240ohm zq +/-1% vtt ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq d9 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ck1 ck1 cke1 odt1 s1 dqs2 dqs2 dm2 dq[16, 23] dqs dqs dm dq d1 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq d10 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs4 dqs4 dm4 dq[32, 39] dqs dqs dm dq d2 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq d11 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs1 dqs1 dm1 dq[8, 15] dqs3 dqs3 dm3 dq[24, 31] dqs5 dqs5 dm5 dq[40, 47] dqs7 dqs7 dm7 dq[56, 63] vtt vtt vdd vdd cterm cterm d13 d4 dqs dqs dm dq 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] d14 d5 dqs dqs dm dq zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm 240ohm d15 d6 dqs dqs dm dq zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm 240ohm dqs6 dqs6 dm6 dq[48, 55] dqs dqs dm dq d3 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq d12 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] d16 d7 dqs dqs dm dq zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm 240ohm v ref dq d0?d17 v dd spd spd/ts d0?d17 v ref ca v tt v tt d0?d17 v dd ck1 d9?d17 cke0 d0?d8 cke0 d9?d17 ck1 d9?d17 ck0 d0?d8 s0 d0?d8 s1 d9?d17 ck0 d0?d8 odt0 d0?d8 odt1 d9?d17 event temp sensor reset d0?d17 dqs8 dqs8 dm8 cb[0, 7] dqs dqs dm dq d8 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq d17 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] notes 1. dq - to - i/o wiring may be changed within a byte 2. zq resistors are 240 ohms +/- 1%. for all other resistor values refer to the appropriate wiring diagram. 3. the connected of the serial pd to event (option 1) or to ground (option 2) is realized by resistor options. a2 sda scl wp a1 a0 scl sa0 sa1 option 2 serial spd sa2 a2 sda scl a1 a0 scl sa0 sa1 option 1 integrated thermal sensor in spd sa2 event event sensor pd w/integrated thermal sensor sensor pd no thermal sensor d0?d17, spd, temp sensor vss
rev. 0.1 / jul. 2012 11 absolute maximum ratings absolute maximum dc ratings notes: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operat ion of the device at these or any other conditions above those indicated in the operational sections of this specif ication is not implied. exposure to absolute maximum rat - ing conditions for extended pe riods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all times; and vref must not be greater than 0.6xvddq,when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. ? dram component operat ing temperature range notes: 1. operating temperature toper is the case surface temperature on the center / top side of the dram. for mea - surement conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatures where all dram specificatio ns will be supported. dur - ing operation, the dram case temperature must be maintained between 0 - 85 o c under all operating conditions. 3. some applications require operation of the dr am in the extended temperature range between 85 o c and 95 o c case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a. refresh commands must be doubled in frequency, theref ore reducing the refresh interval trefi to 3.9 s. it is also possible to specify a component with 1x refres h (trefi to 7.8s) in the extended temperature range. please refer to the dimm spd for option availability b. ddr3l sdrams support auto self-r efresh and extended temperature range and please refer to component datasheet and/or the dimm spd for trefi requ irement in the extended temperature range. absolute maximum dc ratings symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.80 v v 1, vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.80 v v 1, v in , v out voltage on any pin relative to vss - 0.4 v ~ 1.80 v v 1 t stg storage temperature -55 to +100 o c1, 2 temperature range symbol parameter rating units notes t oper normal operating temperature range 0 to 85 o c 1,2 extended temperature range 85 to 95 o c1,3
rev. 0.1 / jul. 2012 12 ac & dc operating conditions recommended dc operating conditions recommended dc operating conditions - ddr3l (1.35v) operation symbol parameter rating units notes min. typ. max. vdd supply voltage 1.283 1.35 1.45 v 1,2,3,4 vddq supply voltage for output 1.283 1.35 1.45 v 1,2,3,4 notes: 1. maximum dc value may not be greater than 1.425v. the dc value is the linear average of vdd/vddq (t) over a very long period of time (e.g., 1 sec). 2. if maximum limit is exceeded, input levels shall be governed by ddr3l specifications. 3. under these supply voltages, the device operates to this ddr3l specification. 4. once initialized for ddr3l operation, ddr3 operation may only be used if the device is in reset while vdd and vddq are changed for ddr3 operation (see figure 0). recommended dc operating condit ions - ddr3 (1.5v) operation symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.5 1.575 v 1,2,3 vddq supply voltage for output 1.425 1.5 1.575 v 1,2,3 notes: 1. if minimum limit is exceeded, input levels shall be governed by ddr3l specifications. 2. under 1.5v operation, this ddr3l device operates to the ddr3 specifications under the same speed timings as defined for this device. 3. once initialized for ddr3 operation, ddr3l operation may only be used if the device is in reset while vdd and vddq are changed for ddr3l operation (see figure 0).
rev. 0.1 / jul. 2012 13 figure 0 - vdd/vddq voltage switch between ddr3l and ddr3 note 1: from time point td until tk nop or des commands must be applied between mrs and zqcl commands. ta ck,ck# reset# tb tc td te tf tg th ti tj tk mrs 1) 1) mrs mrs cke don t care read mrs t = 500us command odt ba rtt mr3 mr1 mr0 read mr2 read static low in case rtt_nom is enabled at time tg, otherwise static high or low vdd, vddq (ddr3) vdd, vddq (ddr3l) zqcl valid valid valid valid tmin = 200us tmin = 10ns tmin = 10ns tcksrx tmin = 10ns tis tis tis txpr tmrd tmrd tmrd tmod tzqinit tdllk time break
rev. 0.1 / jul. 2012 14 ac & dc input measurement levels ac and dc logic input levels for single-ended signals ac and dc input levels for single -ended command and address signals notes: 1. for input only pins except reset , vref = vrefca (dc). 2. refer to "overshoot and undershoot specifications" on page 27. 3. the ac peak noise on v ref may not allow v ref to deviate from v refca(dc) by more than +/-1% vdd (for reference: approx. +/- 13.5 mv). 4. for reference: approx. vdd/2 +/- 13.5 mv 5. these levels apply for 1.35 volt (see table above) operation only. if the device is operated at 1.5v (table "single ended ac and dc input levels for dq and dm " on page 15), the respective levels in jesd79-3 (vih/l.ca(dc100), vih/l.ca(ac175), vih/l.ca(ac150), vih/l.ca(ac135), vih/l.ca(ac125) etc.) apply. the 1.5v levels (vih/l.ca(dc100), vih/l.ca(a c175), vih/l.ca(ac150), vih/l.ca(ac135), vih/ l.ca(ac125) etc.) do not apply when the devi ce is operated in the 1.35 voltage range. single ended ac and dc input levels for command and address symbol parameter ddr3l-800/1066 ddr3l-1333/1600 unit notes min max min max vih.ca(dc90) dc input logic high vref + 0.09 vdd vref + 0.09 vdd v 1 vil.ca(dc90) dc input logic low vss vref - 0.09 vss vref - 0.09 v 1 vih.ca(ac160) ac input logic high vref + 0.160 note2 vref + 0.160 note2 v 1,2,5 vil.ca(ac160) ac input logic low note2 vref - 0.160 note2 vref - 0.160 v 1,2,5 vih.ca(ac135) ac input logic high vref + 0.135 note2 vref + 0.135 note2 v 1,2,5 vil.ca(ac135) ac input logic low note2 vref - 0.135 note2 vref - 0.135 v 1,2,5 vih.ca(ac125) ac input logic high ----v1,2,5 vil.ca(ac125)ac input logic low----v1,2,5 v refca(dc ) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd 0.49 * vdd 0.51 * vdd v 3,4
rev. 0.1 / jul. 2012 15 ac and dc input levels for single-ended signals ddr3 sdram will support two vih/vil ac levels fo r ddr3-800 and ddr3-1066s specified in table below. ddr3 sdram will also support corresponding tds valu es (table 43 on page 117 and table 50 on page 142 in ?ddr3l device operation?) as well as derating tables table 46 on page 135 in ?ddr3l device opera- tion? depending on vih/vil ac levels. notes: 1. vref = vrefdq (dc). 2. refer to "overshoot and undershoot specifications" on page 27. 3. the ac peak noise on v ref may not allow v ref to deviate from v refdq(dc) by more than +/-1% vdd (for reference: approx. +/- 13.5 mv). 4. for reference: approx. vdd/2 +/- 13.5 mv 4. for reference: approx. vdd/2 +/- 13.5 mv 5. these levels apply for 1.35 volt (table "singl e ended ac and dc input levels for command and address" on page 14) operation only. if the device is operated at 1.5v (table ab ove), the respective levels in jesd79-3 (vih/l.dq(dc100), vih/l.dq(ac175), vih/ l.dq(ac150), vih/l.dq(ac135) etc.) apply. the 1.5v levels (vih/l.dq(dc100), vih/l.dq(ac175), vih/ l.dq(ac150), vih/l.dq(ac135) etc.) do not apply when the device is operated in the 1.35 voltage range. single ended ac and dc input levels for dq and dm symbol parameter ddr3l-800/1066 ddr3l-1333/1600 unit notes min max min max vih.dq(dc90) dc input logic high vref + 0.09 vdd vref + 0.09 vdd v 1 vil.dq(dc90) dc input logic low vss vref - 0.09 vss vref - 0.09 v 1 vih.dq(ac160) ac input logic high vref + 0.160 note2 - - v 1, 2, 5 vil.dq(ac160) ac input logic low note2 vref - 0.160 - - v 1, 2, 5 vih.dq(ac135) ac input logic high vref + 0.135 note2 vref + 0.135 note2 v 1, 2, 5 vil.dq(ac135) ac input logic low note2 vref - 0.135 note2 vref - 0.135 v 1, 2, 5 vih.dq(ac130) ac input logic high - - - - v 1, 2, 5 vil.dq(ac130) ac input logic low - - - - v 1, 2, 5 v refdq(dc ) reference voltage for dq, dm inputs 0.49 * vdd 0.51 * vdd 0.49 * vdd 0.51 * vdd v 3, 4
rev. 0.1 / jul. 2012 16 vref tolerances the dc-tolerance limits and ac-noise limits for the reference voltages vrefca and v refdq are illustrated in figure below. it shows a valid reference voltage v ref (t) as a function of time. (v ref stands for v refca and v refdq likewise). v ref (dc) is the linear average of v ref (t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in the table "different ial input slew rate defini tion" on page 22. further- more v ref (t) may temporarily deviate from v ref (dc) by no more than +/- 1% vdd. illustration of v ref(dc) tolerance and v ref ac-noise limits the voltage levels for setup and hold time measurements v ih(ac) , v ih(dc) , v il(ac) , and v il(dc) are depen- dent on v ref . ?v ref ? shall be understood as v ref(dc) , as defined in figure above. this clarifies that dc-variations of v ref affect the absolute voltage a sign al has to reach to achieve a valid high or low level and therefore the time to which se tup and hold is measured. system timing and voltage budgets need to account for v ref(dc) deviations from the optimum position within the data-eye of the input signals. this also clarifies that the dram setup/hold specific ation and derating values need to include time and voltage associated with v ref ac-noise. timing and voltage effects due to ac-noise on v ref up to the speci- fied limit (+/- 1% of vdd) are included in dram timings and their associated deratings. vdd vss vdd/2 v ref(dc) v ref ac-noise voltage time v ref(dc)max v ref(dc)min v ref (t)
rev. 0.1 / jul. 2012 17 ac and dc logic input levels for differential signals differential signal definition definition of differential ac-swi ng and ?time above ac-level? t dvac time differential input voltage(i.e.dqs - dqs#, ck - ck#) v il.diff.ac.max v il.diff.max 0 v il.diff.min v il.diff.ac.min t dvac half cycle t dvac
rev. 0.1 / jul. 2012 18 differential swing requirem ents for clock (ck - ck ) and strobe (dqs-dqs ) notes: 1. used to define a differential signal slew-rate. 2. for ck - ck use vih/vil (ac) of aadd/cmd and vrefca; for dqs - dqs , dqsl, dqsl , dqsu, dqsu use vih/vil (ac) of dqs and vrefdq; if a reduced ac-high or ac-low le vels is used for a signal group, then the reduced level applies also here. 3. these values are not defined; however, the single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (vih (dc) max, vil (dc) min) for sing le-ended signals as well as the limita - tions for overshoot and undershoot. refer to "overshoot and undershoot specifications" on page 27. note : rising input signal shall become equal to or greate r than vih(ac) level and fallin g input signal shall become equal to or less than vil(ac) level. differential ac and dc input levels symbol parameter ddr3l-800, 1066, 1333, & 1600 unit notes min max vihdiff differential input high + 0.180 note 3 v 1 vildiff differential input logic low note 3 - 0.180 v 1 vihdiff (ac) differential input high ac 2 x (vih (ac) - vref) note 3 v 2 vildiff (ac) differential input low ac note 3 2 x (vil (ac) - vref) v 2 allowed time before ringback (tdvac) for ck - ck and dqs - dqs slew rate [v/ns] ddr3l-800/106 6/1333/1600 tdvac [ps] @ |vih/ldiff (ac)| = 320mv tdvac [ps] @ |vih/ldiff (ac)| = 270mv min max min max > 4.0 189 - 201 - 4.0 189 - 201 - 3.0 162 - 179 - 2.0 109 - 134 1.8 91 - 119 - 1.6 69 - 100 - 1.4 40 - 76 - 1.2 note - 44 - 1.0 note - note - < 1.0 note - note -
rev. 0.1 / jul. 2012 19 single-ended requirements for differential signals each individual component of a differen tial signal (ck, dqs, dqsl, dqsu, ck , dqs , dqsl , of dqsu ) has also to comply with certain requ irements for single-ended signals. ck and ck have to approximately reach vsehmin / vselmax (approximately equal to the ac-levels (vih (ac) / vil (ac)) for add/cmd signals) in every half-cycle. dqs, dqsl, dqsu, dqs , dqsl have to reach vsehmin / vselmax (a pproximately the ac-levels (vih (ac) / vil (ac)) for dq signals) in every half-cyc le preceding and following a valid transition. note that the applicable ac-levels for add/cmd and dq ?s might be different per speed-bin etc. e.g., if vih.ca(ac150)/vil.ca(ac150) is used for add/cmd signal s, then these ac-levels apply also for the single- ended signals ck and ck . single-ended requirements for differential signals. note that, while add/cmd and dq signal requirements are with respect to vref, the single-ended compo- nents of differential signals have a requirement with respect to vdd / 2; this is nominally the same. the transition of single-ended signals through the ac-lev els is used to measure se tup time. for single-ended components of differential signals the requirement to reach vselmax, vsehmin ha s no bearing on timing, but adds a restriction on the common mode characteristics of these signals. vdd or vddq vsehmin vdd/2 or vddq/2 vseh vselmax vss or vssq ck or dqs vsel time
rev. 0.1 / jul. 2012 20 notes: 1. for ck, ck use vih/vil (ac) of add/cmd; for strobes (dqs, dqs , dqsl, dqsl , dqsu, dqsu ) use vih/vil (ac) of dqs. 2. vih (ac)/vil (ac) for dqs is based on vrefdq; vih (ac) /vil (ac) for add/cmd is based on vrefca; if a reduced ac-high or ac-low level is used for a signal gr oup, then the reduced level applies also here. 3. these values are not defined; however, the single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (vih (dc) max, vil (dc) min) for sing le-ended signals as well as the limita - tions for overshoot and undershoot. refer to "overshoot and undershoot specifications" on page 27. single-ended levels for ck, dqs, dqsl, dqsu, ck , dqs , dqsl or dqsu symbol parameter ddr3l-800, 1066, 1333 unit notes min max vseh single-ended high level for strobes (vdd / 2) + 0.175 note 3 v 1,2 single-ended high level for ck, ck (vdd /2) + 0.175 note 3 v 1,2 vsel single-ended low level for strobes note 3 (vdd / 2) = 0.175 v 1,2 single-ended low level for ck, ck note 3 (vdd / 2) = 0.175 v 1,2
rev. 0.1 / jul. 2012 21 differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements in table below. the differential input cross point voltage vix is measured from the actual cross point of true and complement signal s to the midlevel between of vdd and vss vix definition notes: 1. the relation between vix min/max a nd vsel/vseh should satisfy following. ? (vdd/2) + vix (min) - vsel ? 25mv ? vseh - ((vdd/2) + vix (max)) ? 25mv cross point voltage for differential input signals (ck, dqs) symbol parameter ddr3l-800, 1066, 1333, 1600 unit notes min max v ix differential input cross point voltage relative to vdd/2 for ck, ck -150 150 mv 1 v ix differential input cross point voltage relative to vdd/2 for dqs, dqs -150 150 mv 1
rev. 0.1 / jul. 2012 22 slew rate definitions for single-ended input signals see 7.5 ?address / command setup, hold and derating? on page 138 in ?ddr3l device operation? for sin- gle-ended slew rate definitions for address and command signals. ? see 7.6 ?data setup, hold and slew rate derating? on page 145 in ?ddr3l device operation? for single- ended slew rate definition for data signals. slew rate definitions for differential input signals input slew rate for differential signals (ck, ck and dqs, dqs ) are defined and measur ed as shown in table and figure below. notes: the differential signal (i.e. ck-ck and dqs-dqs ) must be linear between these thresholds. di fferential input slew rate definition for dqs, dqs and ck, ck differential input slew rate definition description measured defined by min max differential input slew rate for rising edge (ck-ck and dqs-dqs ) vildiffmax vihdiffmin [vihdiffmi n-vildiffmax] / deltatrdiff differential input slew rate for falling edge (ck-ck and dqs-dqs ) vihdiffmin vildiffmax [vihdiffmi n-vildiffmax] / deltatfdiff delta tfdiff delta trdiff vihdiffmin vildiffmax 0 differential input voltag e (i.e. dqs-dqs; ck-ck) differential input slew rate definition for dqs, dqs# and ck, ck#
rev. 0.1 / jul. 2012 23 ac & dc output measurement levels single ended ac and dc output levels table below shows the output levels used for measurements of single ended signals. notes: 1. the swing of 0. 1 x v ddq is based on approximately 50% of the st atic single ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to v tt = v ddq / 2. differential ac and dc output levels table below shows the output levels used for measurements of single ended signals. notes: 1. the swing of 0.2 x v ddq is based on approximately 50% of the st atic differential output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to v tt = v ddq /2 at each of the differential outputs. single-ended ac and dc output levels symbol parameter ddr3l-800, 1066, 1333 and 1600 unit notes v oh(dc) dc output high measurement level (for iv curve linearity) 0.8 x v ddq v v om(dc) dc output mid measurement level (for iv curve linearity) 0.5 x v ddq v v ol(dc) dc output low measurement le vel (for iv curve linearity) 0.2 x v ddq v v oh(ac) ac output high measurement level (for output sr) v tt + 0.1 x v ddq v1 v ol(ac) ac output low measurement level (for output sr) v tt - 0.1 x v ddq v1 differential ac and dc output levels symbol parameter ddr3l-800, 1066, 1333 and 1600 unit notes v ohdiff (ac) ac differential output high measurement level (for output sr) + 0.2 x v ddq v1 v oldiff (ac) ac differential output low measurement level (for output sr) - 0.2 x v ddq v1
rev. 0.1 / jul. 2012 24 single ended ou tput slew rate when the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between v ol(ac) and v oh(ac) for single ended signals are sh own in table and figure below. notes: 1. output slew rate is verified by design and charac terisation, and may not be su bject to production test. single ended output slew rate definition description: sr; slew rate q: query output (like in dq, which stands for data-in, query-output) se: single-ended signals for ron = rzq/7 setting note 1): in two cases, a maximum slew rate of 6v/ns applies for a single dq signal within a byte lane. case 1 is a defined for a single dq signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining dq signals in the same byte lane are static (i.e. they stay at either high or low). case 2 is a defined for a single dq signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining dq signals in the same byte lane switching into the opposite direction (i.e. from low to high of high to low respectively). for the remaining dq signal switching in to the opposite direction, the regular maximum limite of 5 v/ns applies. single-ended output slew rate definition description measured defined by from to single-ended output slew rate for rising edge v ol(ac) v oh(ac) [v oh(ac) -v ol(ac) ] / deltatrse single-ended output slew rate for falling edge v oh(ac) v ol(ac) [v oh(ac) -v ol(ac) ] / deltatfse output slew rate (single-ended) ddr3l-800 ddr3l-1066 ddr3l-1333 ddr3l-1600 units parameter symbol min max min max min max min max single-ended output slew rate srqse 1.75 5 1) 1.75 5 1) 1.75 5 1) 1.75 5 1) v/ns delta tfse delta trse voh(ac) vol(ac) v single ended output voltage(l.e.dq) single ended output slew rate definition
rev. 0.1 / jul. 2012 25 differential output slew rate with the reference load for timing measurements, output slew rate for falling an d rising edges is defined and measured between voldiff (ac) and vohdiff (ac) fo r differential signals as shown in table and figure below. differential output slew rate definition differential output slew rate definition description measured defined by from to differential output slew rate for rising edge v oldiff (ac) v ohdiff (ac) [v ohdiff (ac) -v oldiff (ac) ] / deltatrdiff differential output slew rate for falling edge v ohdiff (ac) v oldiff (ac) [v ohdiff (ac) -v oldiff (ac) ] / deltatfdiff notes: 1. output slew rate is verified by design and charac terization, and may not be subject to production test. differential output slew rate ddr3l-800 ddr3l-1066 ddr3l-1333 ddr3l-1600 units parameter symbol min max min max min max min max differential output slew rate srqdiff 3.5 12 3.5 12 3.5 12 3.5 12 v/ns description: sr; slew rate q: query output (like in dq, which stands for data-in, query-output) se: single-ended signals for ron = rzq/7 setting delta tfdiff delta trdiff vohdiff(ac) voldiff(ac) o differential output voltage(i.e. dqs-dqs) differential output slew rate definition
rev. 0.1 / jul. 2012 26 reference load for ac timing and output slew rate figure below represents the effective reference load of 25 ohms used in defining the relevant ac timing parameters of the device as well as output slew rate measurements. it is not intended as a precise representation of an y particular system environment or a depiction of the actual load presented by a production tester. system de signers should use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers correlate to their production test conditions, generally one or more coaxial transm ission lines terminated at the tester electronics. reference load for ac timing and output slew rate dut dq dqs dqs vddq 25 ohm vtt = vddq/2 ck, ck
rev. 0.1 / jul. 2012 27 overshoot and unders hoot specifications address and control overshoot and undershoot specifications address and control overshoo t and undershoot definition ac overshoot/undershoot specification for address and control pins parameter ddr3l- 800 ddr3l- 1066 ddr3l- 1333 ddr3l- 1600 units maximum peak amplitude allowed for overshoo t area. (see figure below) 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoot area. (see figure below) 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd (see figure below) 0.67 0.5 0.4 0.33 v-ns maximum undershoot area below vss (see figure below) 0.67 0.5 0.4 0.33 v-ns (a0-a15, ba0-ba3, cs , ras , cas , we , cke, odt) see figure below for each parameter definition maximum amplitude overshoot area vdd vss maxim um am plitude undershoot area time (ns) address and control overshoot and undershoot definition volts (v)
rev. 0.1 / jul. 2012 28 clock, data, strobe and mask over shoot and undershoot specifications clock, data, strobe and mask ov ershoot and undershoot definition ac overshoot/undershoot specificatio n for clock, data, strobe and mask parameter ddr3l- 800 ddr3l- 1066 ddr3l- 1333 ddr3l- 1600 units maximum peak amplitude allowed for overshoo t area. (see figure below) 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoo t area. (see figure below) 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd (s ee figure below) 0.25 0.19 0.15 0.13 v-ns maximum undershoot area below vss (see figure below) 0.25 0.19 0.15 0.13 v-ns (ck, ck , dq, dqs, dqs , dm) see figure below for each parameter definition maximum amplitude overshoot area vddq vssq m axim um am plitude undershoot area time (ns) clock, data strobe and mask overshoot and undershoot definition volts (v)
rev. 0.1 / jul. 2012 29 refresh parameters by device density refresh parameters by device density parameter rtt_nom setting 512mb 1gb 2gb 4gb 8gb units ref command act or ref command time trfc 90 110 160 260 350 ns average periodic refresh interval trefi 0 ? c ? t case ? 85 ? c 7.8 7.8 7.8 7.8 7.8 us 85 ? c ? t case ? 95 ? c 3.9 3.9 3.9 3.9 3.9 us
rev. 0.1 / jul. 2012 30 standard speed bins ddr3 sdram standard speed bins include tck, trcd , trp, tras and trc for each corresponding bin. ddr3l-800 speed bins for specific notes see "speed bin table notes" on page 34. speed bin ddr3l-800e unit notes cl - nrcd - nrp 6-6-6 parameter symbol min max internal read command to first data t aa 15 20 ns act to internal read or write delay time t rcd 15 ? ns pre command period t rp 15 ? ns act to act or ref command period t rc 52.5 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1,2,3,4,9,10 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3 supported cl settings 5, 6 n ck 10 supported cwl settings 5 n ck
rev. 0.1 / jul. 2012 31 ddr3l-1066 speed bins for specific notes see "speed bin table notes" on page 34. speed bin ddr3l-1066f unit note cl - nrcd - nrp 7-7-7 parameter symbol min max internal read command to first data t aa 13.125 20 ns act to internal read or write delay time t rcd 13.125 ? ns pre command period t rp 13.125 ? ns act to act or ref command period t rc 50.625 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1,2,3,4,6,9,10 cwl = 6 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,6 cwl = 6 t ck(avg) reserved ns 1,2,3,4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3 supported cl settings 5, 6, 7, 8 n ck 10 supported cwl settings 5, 6 n ck
rev. 0.1 / jul. 2012 32 ddr3l-1333 speed bins for specific notes see "speed bin table notes" on page 34. speed bin ddr3l-1333h unit note cl - nrcd - nrp 9-9-9 parameter symbol min max internal read command to first data t aa 13.5 (13.125) 5,8 20 ns act to internal read or write delay time t rcd 13.5 (13.125) 5,8 ?ns pre command period t rp 13.5 (13.125) 5,8 ?ns act to act or ref command period t rc 49.5 (49.125) 5,8 ?ns act to pre command period t ras 36 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1,2,3,4,7,9,10 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,7 cwl = 6 t ck(avg) reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4,7 (optional) 5,8 cwl = 7 t ck(avg) reserved ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,7 cwl = 7 t ck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3 (optional) ns 5 supported cl settings 5, 6, 7, 8, 9, 10 n ck supported cwl settings 5, 6, 7 n ck
rev. 0.1 / jul. 2012 33 ddr3l-1600 speed bins for specific notes see "speed bin table notes" on page 34. speed bin ddr3l-1600k unit note cl - nrcd - nrp 11-11-11 parameter symbol min max internal read command to first data t aa 13.75 (13.125) 5,9 20 ns act to internal read or write delay time t rcd 13.75 (13.125) 5,9 ?ns pre command period t rp 13.75 (13.125) 5,9 ?ns act to act or ref command period t rc 48.75 (48.125) 5,9 ?ns act to pre command period t ras 35 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 3.0 3.3 ns 1,2,3,4,8,10,11 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,8 cwl = 6 t ck(avg) reserved ns 1,2,3,4,8 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4,8 (optional) 5,9 cwl = 7 t ck(avg) reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,8 cwl = 7 t ck(avg) reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,4,8 (optional) 5,9 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,8 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 11 cwl = 5, 6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 <1.5 ns 1,2,3 supported cl settings 5, 6, 7, 8, 9, 10, 11 n ck supported cwl settings 5, 6, 7, 8 n ck
rev. 0.1 / jul. 2012 34 speed bin table notes absolute specification (t oper ; v ddq = v dd = 1.35v +0.100/- 0.067 v); 1. the cl setting and cwl setting result in tck(avg).min and tck(avg).max requirements. when mak - ing a selection of tck(avg), both need to be fulfille d: requirements from cl setting as well as require - ments from cwl setting. 2. tck(avg).min limits: since cas latency is not pure ly analog - data and strobe output are synchro - nized by the dll - all possible intermediate freque ncies may not be guaranteed. an application should use the next smaller jedec standard tck(avg) valu e (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat - ing cl [nck] = taa [ns] / tck(avg) [ns], rounding up to the next ?supported cl?, where tck(avg) = 3.0 ns should only be used for cl = 5 calculation. 3. tck(avg).max limits: calculate tck(avg) = taa.ma x / cl selected and round the resulting tck(avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to cl selected. 4. ?reserved? settings are not allowed. user must program a different value. 5. ?optional? settings allow certain devices in the indust ry to support this setting, however, it is not a man - datory feature. refer to dimm data sheet and/or th e dimm spd information if and how this setting is supported. 6. any ddr3-1066 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production te sts but verified by de sign/characterization. 7. any ddr3-1333 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production te sts but verified by de sign/characterization. 8. any ddr3-1600 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production test s but verified by desi gn/characterization. 9. ddr3 sdram devices supporting optional down binni ng to cl=7 and cl=9, and taa/trcd/trp must be 13.125 ns or lower. spd settings must be programmed to match. for example, ddr3-1333h devices supporting down binning to ddr3-1066f shou ld program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20) . ddr3-1600k devices supporting down binning to ddr3-1333h or ddr3-1600f should program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20). once trp (byte 20) is programmed to 13.125ns, trcmin (byte 21,23) also should be programmed accordingly. for ex ample, 49.125ns (trasmin + trpmin = 36 ns + 13.125 ns) for ddr3-1333h and 48.125ns (trasmin + trpmin = 35 ns + 13.125 ns) for ddr3-1600k. 10. ddr3 800 ac timing apply if dram operat es at lower than 800 mt/s data rate. 11. for cl5 support, refer to dimm spd information. dram is required to support cl5. cl5 is not manda - tory in spd coding.
rev. 0.1 / jul. 2012 35 environmental parameters note : 1. stress greater than those listed may cause permanent damage to the device. this is a stress rating only, and device functional operation at or above the condit ions indicated is not implied. expousure to absolute maximum rating conditions for extended periods may affect reliablility. 2. up to 9850 ft. 3. the designer must meet the case temperature specifications for individual module components. symbol parameter rating units notes t opr operating temperature 0 to 65 o c1, 3 h opr operating humidity (relative) 10 to 90 % 1 t stg storage temperature -50 to +100 o c 1 h stg storage humidity (without condensation) 5 to 95 % 1 p bar barometric pressure (operating & storage) 105 to 69 k pascal 1, 2
rev. 0.1 / jul. 2012 36 idd and iddq specification pa rameters and test conditions idd and iddq measurement conditions in this chapter, idd and iddq measurement conditions such as test load and patt erns are defined. figure 1. shows the setup and test load for idd and iddq measurements. ? idd currents (such as idd0, idd1, idd2n, idd2nt , idd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et and idd7) are measured as time-averaged currents with all vdd balls of the ddr3 sdram under test tied together. any iddq current is not included in idd currents. ? iddq currents (such as iddq2nt and iddq4r) are measured as time-averaged currents with all vddq balls of the ddr3 sdram under test tied toge ther. any idd current is not included in iddq cur - rents. ? attention: iddq values cannot be directly used to calculate io power of the ddr3 sdram. they can be used to support correlation of simulated io power to actual io po wer as outlined in figure 2. in dram module application, iddq cannot be measured separately si nce vdd and vddq are using one merged-power layer in module pcb. for idd and iddq measurements, the following definitions apply: ? ?0? and ?low? is defined as vin <= v ilac(max). ? ?1? and ?high? is defined as vin >= v ihac(max). ? ?mid_level? is defined as inputs are vref = vdd/2. ? timing used for idd and iddq measurement-loop patterns are provided in table 1. ? basic idd and iddq measurement co nditions are described in table 2. ? detailed idd and iddq measurement-loop patte rns are described in table 3 through table 10. ? idd measurements are done after properly initializi ng the ddr3 sdram. this includes but is not lim - ited to setting ? ron = rzq/7 (34 ohm in mr1); ? qoff = 0 b (output buffer enabled in mr1); ? rtt_nom = rzq/6 (40 ohm in mr1); ? rtt_wr = rzq/2 (120 ohm in mr2); ? tdqs feature disabled in mr1 ? attention: the idd and iddq measurement-loop patterns need to be executed at least one time before actual idd or iddq measurement is started. ? define d = { cs , ras , cas , we }:= {high, low, low, low} define d = { cs , ras , cas , we }:= {high, high, high, high}
rev. 0.1 / jul. 2012 37 figure 1 - measurement setup and test load for idd and iddq (optional) measurements [note: dimm level output test load condition may be different from above figure 2 - correlation from simulated channel io power to actual ch annel io power supported by iddq measurement v dd ddr3l sdram v ddq reset ck/ck dqs, dqs cs ras , cas , we a, ba odt zq v ss v ssq dq, dm, tdqs, tdqs cke r tt = 25 ohm v ddq /2 i dd i ddq (optional) application specific memory channel environment channel io power simulation iddq simulation iddq simulation channel io power number iddq test load correction
rev. 0.1 / jul. 2012 38 table 1 -timings used for idd an d iddq measurement-loop patterns table 2 -basic idd and id dq measurement conditions symbol ddr3l-1066 ddr3l-1333 ddr3l-1600 unit 7-7-7 9-9-9 11-11-11 t ck 1.875 1.5 1.25 ns cl 7 9 11 nck n rcd 7911nck n rc 27 33 39 nck n ras 20 24 28 nck n rp 7911nck n faw 1kb page size 20 20 24 nck 2kb page size 27 30 32 nck n rrd 1kb page size 4 4 5 nck 2kb page size 6 5 6 nck n rfc -512mb 48 60 72 nck n rfc -1 gb 59 74 88 nck n rfc - 2 gb 86 107 128 nck n rfc - 4 gb 139 174 208 nck n rfc - 8 gb 187 234 280 nck symbol description i dd0 operating one bank active-precharge current ? cke: high; external clock: on; tck, nrc, nras, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act and pre; command, address, bank address inputs: partiall y toggling according to table 3; data io: mid-level; dm: stable at 0; bank activity: cyclin g with one bank active at a time: 0, 0,1,1,2,2,... (see table 3); output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 3. i dd1 operating one bank active-precharge current cke: high; external clock: on; tck, n rc, nras, nrcd, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act, rd and pre; command, address; bank address inputs, da ta io: partially toggling ac cording to table 4; dm: stable at 0; bank activity: cycling with on bank active at a time: 0,0,1,1,2,2,... (see table 4); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 4.
rev. 0.1 / jul. 2012 39 i dd2n precharge standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd2nt precharge standby odt current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 6; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: toggling according to table 6; pattern details: see table 6. i dd2p0 precharge power-down current slow exit cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks closed; output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at 0; prec harge power down mode: slow exit c) i dd2p1 precharge power-down current fast exit cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks closed; output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at 0; prec harge power down mode: fast exit c) i dd2q precharge quiet standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks closed; output buf- fer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i dd3n active standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks open; output buffer and rt t: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd3p active power-down current cke: low; external clock: on; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 symbol description
rev. 0.1 / jul. 2012 40 i dd4r operating burst read current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between rd; command, address, bank address inputs: partially toggling according to tabl e 7; data io: seamless read data burst with different data between one burst and the next one according to tabl e 7; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,...(see table 7); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 7. i dd4w operating burst write current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between wr; command, address, bank address inputs: partially toggling according to tabl e 8; data io: seamless read data burst with different data between one burst and the next one according to tabl e 8; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,...(see table 8); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at high; pattern details: see table 8. i dd5b burst refresh current cke: high; external clock: on; tck, cl, nrfc: see table 1; bl: 8 a) ; al: 0; cs : high between ref; command, address, bank address inputs: partiall y toggling according to table 9; data io: mid_level; dm: stable at 0; bank activity: ref command every nref (see table 9); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 9. i dd6 self-refresh current: normal temperature range t case : 0 - 85 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: mid_level i dd6et self-refresh current: extended temperature range t case : 0 - 95 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): extended e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: extended temperature self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: mid_level symbol description
rev. 0.1 / jul. 2012 41 a) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b b) output buffer enable: set mr1 a[12] = 0b; set mr1 a[5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b c) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12 = 1b for fast exit d) auto self-refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature e) self-refresh temperature range (srt): set mr2 a7 = 0b for normal or 1b for extended temperature range f) read burst type: nibble sequential, set mr0 a[3] = 0b i dd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nr as, nrcd, nrrd, nfaw, cl: see table 1; bl: 8 a,f) ; al: cl-1; cs : high between act and rda; command, address, bank a ddress inputs: partially togg ling according to table 10; data io: read data burst with different data betw een one burst and the next one according to table 10; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1,.. .7) with different address- ing, wee table 10; output buffer an d rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 10. symbol description
rev. 0.1 / jul. 2012 42 table 3 - idd0 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 0 0 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until n rc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1, 2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3, 4 d , d 1111 0 0000 0 f 0 - ... repeat pattern 1...4 until 1*nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern 1...4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 0.1 / jul. 2012 43 table 4 - idd1 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid- level. b) burst sequence driven on each dq signal by re ad command. outside burst operation, dq signals are mid_level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act001100000000 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 111100000000 - ... repeat pattern 1...4 until nrcd - 1, truncate if necessary nrcd rd 0 1 0 1 0 0 00 0 0 0 0 00000000 ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre001000000000 - ... repeat pattern 1...4 until nr c - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1,2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3,4 d , d 1111000000f0 - ... repeat pattern nrc + 1,. ..4 until nrc + nrce - 1, truncate if necessary 1*nrc+nrcd rd 0 1 0 1 0 0 00 0 0 f 0 00110011 ... repeat pattern nrc + 1, ...4 until nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern nrc + 1, ...4 until *2 nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 0.1 / jul. 2012 44 table 5 - idd2n and idd3n measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. table 6 - idd2nt and iddq2n t measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 111 1 0 0 0 0 0 f 0 - 3d 111 1 0 0 0 0 0 f 0 - 1 4-7 repeat sub-loop 0, use ba[2:0] = 1 instead 2 8-11 repeat sub-loop 0, use ba[2:0] = 2 instead 3 12-15 repeat sub-loop 0, use ba[2:0] = 3 instead 4 16-19 repeat sub-loop 0, use ba[2:0] = 4 instead 5 20-23 repeat sub-loop 0, use ba[2:0] = 5 instead 6 24-17 repeat sub-loop 0, use ba[2:0] = 6 instead 7 28-31 repeat sub-loop 0, use ba[2:0] = 7 instead ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 1111 0 0 0 0 0 f 0 - 3d 1111 0 0 0 0 0 f 0 - 1 4-7 repeat sub-loop 0, but odt = 0 and ba[2:0] = 1 2 8-11 repeat sub-loop 0, but odt = 1 and ba[2:0] = 2 3 12-15 repeat sub-loop 0, but odt = 1 and ba[2:0] = 3 4 16-19 repeat sub-loop 0, but odt = 0 and ba[2:0] = 4 5 20-23 repeat sub-loop 0, but odt = 0 and ba[2:0] = 5 6 24-17 repeat sub-loop 0, but odt = 1 and ba[2:0] = 6 7 28-31 repeat sub-loop 0, but odt = 1 and ba[2:0] = 7
rev. 0.1 / jul. 2012 45 table 7 - idd4r and iddq4r measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid-level. table 8 - idd4w measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise mid-level. b) burst sequence driven on each dq signal by write co mmand. outside burst operation, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 rd 0 1 0 1 0 0 00 0 0 0 0 00000000 1d100000000000- 2,3 d ,d 1111 0 0000 0 0 0 - 4 rd 0 1 0 1 0 0 00 0 0 f 0 00110011 5d1000000000f0- 6,7 d ,d 1111 0 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 wr 0 1 0 0 1 0 00 0 0 0 0 00000000 1d100010000000- 2,3 d ,d 1111 1 0000 0 0 0 - 4 wr 0 1 0 0 1 0 00 0 0 f 0 00110011 5d1000100000f0- 6,7 d ,d 1111 1 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7
rev. 0.1 / jul. 2012 46 table 9 - idd5b measur ement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 ref 0 0 0 1 0 0 0 0 0 0 0 - 11.2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 f 0 - 5...8 repeat cycles 1...4, but ba[2:0] = 1 9...12 repeat cycles 1...4, but ba[2:0] = 2 13...16 repeat cycles 1...4, but ba[2:0] = 3 17...20 repeat cycles 1...4, but ba[2:0] = 4 21...24 repeat cycles 1...4, but ba[2:0] = 5 25...28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc-1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary.
rev. 0.1 / jul. 2012 47 table 10 - idd7 meas urement-loop pattern a) attention! sub-loops 10-19 have inverse a[6:3] pattern and data pattern than sub-loops 0-9 a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1 rda 0 1 0 1 0 0 00 1 0 0 0 00000000 2 d 1 0 0 0 0 0 00 0 0 0 0 - ... repeat above d command until nrrd - 1 1 nrrd act 0 0 1 1 0 1 00 0 0 f 0 - nrrd+1 rda 0 1 0 1 0 1 00 1 0 f 0 00110011 nrrd+2 d 1 0 0 0 0 1 00 0 0 f 0 - ... repeat above d command until 2* nrrd - 1 2 2*nrrd repeat sub-loop 0, but ba[2:0] = 2 3 3*nrrd repeat sub-loop 1, but ba[2:0] = 3 4 4*nrrd d 1 0 0 0 0 3 00 0 0 f 0 - assert and repeat abov e d command until nfaw - 1, if necessary 5 nfaw repeat sub-loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub-loop 1, but ba[2:0] = 5 7 nfaw+2*nrrd repeat sub-loop 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub-loop 1, but ba[2:0] = 7 9 nfaw+4*nrrd d 1 0 0 0 0 7 00 0 0 f 0 - assert and repeat abov e d command until 2* nfaw - 1, if necessary 10 2*nfaw+0 act 0 0 1 1 0 0 00 0 0 f 0 - 2*nfaw+1 rda 0 1 0 1 0 0 00 1 0 f 0 00110011 2&nfaw+2 d 1 0 0 0 0 0 00 0 0 f 0 - repeat above d command until 2* nfaw + nrrd - 1 11 2*nfaw+nrrd act 0 0 1 1 0 1 00 0 0 0 0 - 2*nfaw+nrrd+1 rda 0 1 0 1 0 1 00 1 0 0 0 00000000 2&nfaw+nrrd+2 d 1 0 0 0 0 1 00 0 0 0 0 - repeat above d command until 2* nfaw + 2* nrrd - 1 12 2*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 2 13 2*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 3 14 2*nfaw+4*nrrd d 1 0 0 0 0 3 00 0 0 0 0 - assert and repeat abov e d command until 3* nfaw - 1, if necessary 15 3*nfaw repeat sub-loop 10, but ba[2:0] = 4 16 3*nfaw+nrrd repeat sub-loop 11, but ba[2:0] = 5 17 3*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 6 18 3*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 7 19 3*nfaw+4*nrrd d 1 0 0 0 0 7 00 0 0 0 0 - assert and repeat abov e d command until 4* nfaw - 1, if necessary
rev. 0.1 / jul. 2012 48 idd specifications (tcase: 0 to 95 o c) * module idd values in the datasheet are only a calculation based on the component idd spec. ? the actual measurements may vary according to dq loading cap. 2gb, 256m x 72 so-d imm: HMT325A7CFR8A 4gb, 512m x 72 so-d imm: hmt351a7cfr8a symbol ddr3l 1066 ddr3l 1333 ddr3l 1600 unit note idd0 315 360 360 ma idd1 405 405 450 ma idd2n 153 162 180 ma idd2nt 180 207 225 ma idd2p0 90 90 90 ma idd2p1 117 117 135 ma idd2q 162 180 180 ma idd3n 180 198 225 ma idd3p 108 117 135 ma idd4r 585 720 810 ma idd4w 585 675 765 ma idd5b 990 1035 1035 ma idd6 90 90 90 ma idd6et 108 108 108 ma idd7 1215 1485 1530 ma symbol ddr3l 1066 ddr3l 1333 ddr3l 1600 unit note idd0 468 522 585 ma idd1 558 567 675 ma idd2n 306 324 360 ma idd2nt 360 414 450 ma idd2p0 180 180 180 ma idd2p1 234 234 270 ma idd2q 324 360 360 ma idd3n 360 396 450 ma idd3p 216 234 270 ma idd4r 738 882 1035 ma idd4w 738 837 990 ma idd5b 1143 1197 1260 ma idd6 180 180 180 ma idd6et 216 216 216 ma idd7 1368 1647 1755 ma
rev. 0.1 / jul. 2012 49 module dimensions 256mx72 - HMT325A7CFR8A front back spd 30.0mm 67.60mm 20.0mm 6.00 2.0 21.00 39.00 2.15 3.00 pin 1 pin 203 detail-a 4.00 0.10 ? 1.65 0.10 ? 1.80 0.10 ? 2 x ? note : 1. tolerance on all dimensions unless otherwise stated. 0.13 ? units: millimeters 2.55 1.00 detail of contacts a 0.3 0.3~1.0 0.15 ? 0.05 ? 0.45 0.03 ? 4.00 0.10 ? 0.60 3.80mm max 1.00 mm 0.08 ? side
rev. 0.1 / jul. 2012 50 512mx72 - hmt351s6cfr8a front back spd 30.0mm 67.60mm 20.0mm 6.00 2.0 21.00 39.00 2.15 3.00 pin 1 pin 203 detail-a 4.00 0.10 ? 1.65 0.10 ? 1.80 0.10 ? 2 x ? note : 1. tolerance on all dimensions unless otherwise stated. 0.13 ? units: millimeters 2.55 1.00 detail of contacts a 0.3 0.3~1.0 0.15 ? 0.05 ? 0.45 0.03 ? 4.00 0.10 ? 0.60 3.80mm max 1.00 mm 0.08 ? side

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